1. Field
The disclosed technology generally relates to semiconductor-on-insulator (SOT) devices and more particularly to SOI devices having a channel region comprising a Group III-V or a Group IV semiconductor material, and also relates to methods of fabricating the same.
The present disclosure also relates to a SOI wafer suitable for manufacturing such semiconductor-on-insulator devices.
The present disclosure also relates to a donor wafer for manufacturing a semiconductor-on-insulator wafer and associated SOI devices.
2. Description of the Related Technology
The semiconductor industry has been considering materials other than silicon (Si) as a base semiconductor material for various integrated circuit devices, in order to maintain or improve their cost and performance, as well as providing scaling options for future technology nodes. Possible candidates to replace or add to Si as the base semiconductor material, e.g., as channel material for transistor devices include other semiconductor materials of group IV, e.g., germanium (Ge) and silicon-germanium (SiGe), and compound semiconductors, e.g., group III-V alloy semiconductor materials (also referred to herein as III-V materials). To be cost-competitive, III-V materials should be capable of being monolithically integrated with Si, in order to benefit from various existing Si-based semiconductor processing techniques and infrastructure. The use of Si as a substrate would also enable the integration of several functional blocks on the same platform, such as for example logic, high-frequency, and 110 circuitry.
The integration of III-V materials on a Si platform, however, poses various technological challenges, e.g., defects arising from the integration. Some defects may arise, for example, from a lattice mismatch between silicon and various III-V materials or between the various III-V materials themselves, such as, e.g., anti-phase boundaries, mismatch stress relaxation, threading dislocations and stacking faults, to name a few.
One approach of integrating III-V materials on a Si platform is a technology referred to as III-V-on-insulator (III-V-OI) technology, which has been suggested as a promising technology for advanced CMOS applications for 1×nm technology node and beyond.
Some methods of fabricating III-V-OI structures have been described Takagi et al in the article “III-V-on-Insulator MOSFETs on Si substrates fabricated by direct wafer bonding” in ECS Transactions, 33 (4) p.359-370 (2010). A first method involves direct growth of III-V materials on Si substrates. This method has the disadvantage of using thick buffer layers (on the order of 1 μm and more) in order to keep the crystal quality of the III-V layer as high as possible and the defect level at the interface as low as possible. The use of thick buffer layers (also often referred to strain relaxed buffer (SRB) layers) is moreover very expensive. A second method is known as direct wafer bonding (DWB). In this approach, an InGaAs layer is thereby formed on a 2 inch InP donor wafer. A buried oxide (BOX) layer of SiO2 is then deposited on the InGaAs/InP. The SiO2/InGaAs/InP wafer is then bonded in air to a Si handling wafer. The InP donor wafer is thereafter removed resulting in a III-V-OI on Si substrate wafer which may be further processed.
This method has the disadvantage that the use of 2 inch III-V donor wafers is not a feasible solution for the 1×nm technology node and beyond, which will be based on substrate platforms that are at least 12 inches (300 mm). Moreover, 2 inch III-V donor wafers can be prohibitively expensive.